1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device (IC package) having a semiconductor chip encapsulated with a package comprised of a resin and being capable of suppressing radiation noise or ground bounce noise caused by a connection wiring structure between the semiconductor chip and the package.
2. Related Background Art
In recent years, with the progress of semiconductor fine processing technology involving further enlargement of circuit scale, the adverse affect of radiation noise or ground bounce noise generated from a semiconductor integrated circuit device (IC) on other electronic devices and malfunction of a circuit itself has become a large problem.
The radiation noise or ground bounce noise is caused by the fact that when an internal circuit of an IC operates, a large current flows through a path of a power terminal of a bypass capacitor→a power line of a printed wiring board→a power line of a package→a power line of a semiconductor chip→an internal load (semiconductor integrated circuit unit)→a ground line of the semiconductor chip→a ground line of the package→a ground line of the printed wiring board→a ground terminal of the bypass capacitor. Specifically, due to an inductance component of the path, a potential variation occurs which is expressed by an equation: ΔV=−L·di/dt, where ΔV is an amount of the potential variation, L is an inductance value, and di/dt is an amount of current variation per unit time. This potential variation directly works as ground bounce to thereby cause malfunction of the circuit, or propagates directly to a main power wiring on the printed wring board or to a signal input/output line (signal line) of the IC to be radiated as radiation noise.
Accordingly, in order to suppress the radiation noise, making the impedance of the current path extending from the bypass capacitor to the semiconductor chip as small as possible is a very important subject. With regard to this subject, Japanese Patent Application Laid-Open Nos. H05-160333 and H09-22977 disclose that power supply lines (ground line and power line) of a package connected to a plurality of electrode pads for wire bonding (wire bonding pads) are made common to each other and led out with a large width.
Further, with the progress of semiconductor fine processing technology involving further enlargement of circuit scale, the size of an outer peripheral region of a semiconductor chip having wire bonding pads disposed therein becomes smaller, and at the same time the number of electrode pads becomes larger. Consequently, there has been adopted a structure in which wire bonding pads are arranged in two rows in a staggered (or zigzag) manner, instead of the arrangement in a single row adopted in the prior art. Japanese Patent Application Laid-Open No. H11-87399 discloses that in this staggered arrangement, for the purpose of stabilizing the characteristic impedance of a signal line and securing power supply to the circuit, a signal pad and a power supply pad (power pad and ground pad) are disposed as one set.
FIG. 7 shows a conventional example, and is a plan view showing the inside of an IC. Wire bonding pads 112 on a semiconductor chip 111 are disposed in two rows in a staggered manner. Of the wire bonding pads 112, wire bonding pads 112a are assigned to a front row that is located less inside of the semiconductor chip 111, and wire bonding pads 112b are assigned to a rear row that is located more inside of the semiconductor chip 111. Lines 113a from the wire bonding pads 112a of the front row, and lines 113b from the wire bonding pads 112b of the rear row are connected to a semiconductor integrated circuit unit (not shown) disposed inside the semiconductor chip 111. In this case, the lines 113a are disposed so as to pass between the wire bonding pads 112b of the rear row. The wire bonding pads 112a and 112b are used as signal pads or power supply pads.
Similarly, wire bonding pads 116 on a package 115 connected via bonding wires 114 to the semiconductor chip 111 are also disposed in two rows in a staggered manner. Of the wire bonding pads 116, wire bonding pads 116a are assigned to a rear row that is located more inside of the package 115, and wire bonding pads 116b are assigned to a front row that is located less inside of the package 115. Lines 117a from the wire bonding pads 116a of the rear row, and lines 117b from the wire bonding pads 116b of the front row are connected to lead pins or BGA ball lands (not shown) used to connect to the outside of the package 115. In this case, the lines 117b are disposed so as to pass between the wire bonding pads 116a in the rear row. The wire bonding pads 116a and 116b are used as signal pads or power supply pads.
However, in such an IC as shown in FIG. 7, when wire bonding pads 112a assigned to the front row located outside of the rear row are used as power supply pads, a power supply line 113a must pass between two signal pads 112b. Thus, the line width of the power supply line of the package cannot exceed the distance between two power supply pads 112b. Similarly, when wire bonding pads 116b assigned to the front row located outside of the rear row of the package 115 are used as power supply pads, the line width of the power supply line 117b cannot exceed the distance between two power supply pads 116a. Accordingly, the impedance of the power supply lines 113a and 117b cannot be lowered, thus restricting the reduction of impedance of the current path of the entire IC. Consequently, there has been posed a problem that much radiation noise and ground bounce noise will be generated.